1. Field of the Invention
This invention relates to a chemical mechanical polishing (CMP) applied in forming shallow trench isolation (STI), and more particularly, to a process of forming a STI structure combining CMP, using a partial reverse active mask.
2. Description of Related Art
CMP is now a technique ideal for applying in global planarization in very large scale integration (VLSI) and even in ultra large scale integration (ULSI). Moreover, CMP is likely to be the only reliable technique as the feature size of the integrated circuit (IC) is highly reduced. Therefore, it is of great interest to develop and improve the CMP technique in order to cut down the cost.
As the IC devices are continuously sized down to a linewidth of 0.25 μm or even 0.18 μm (deep sub-half micron), using CMP to planarize the wafer surface, especially to planarize the oxide layer on the surface of the shallow trench, becomes even more important. To prevent the dishing effect occurring at the surface of a larger trench during CMP process and to obtain a superior CNDP uniformity, a reverse tone active mask was proposed, cooperating with an etching back process.
Typically, the active regions have varied sizes and the shallow trenches between the active regions also have different sizes. FIG. 1A to FIG. 1E are cross-sectional views showing the process steps for forming shallow trench isolation, using CMP. Referring to FIG. 1A, on a substrate 10, a pad oxide 15 and a silicon nitride layer 16 are deposited successively. By photolithography, the substrate 10, the pad oxide layer 15 and the silicon nitride layer 16 are anisotropically etched to form shallow trenches 14a, 14b, 14c and define active regions 12a, 12b, 12c, 12d. The sizes of the shallow trenches 14a, 14b, 14c are different since the sizes of the active regions 12a, 12b, 12c, 12d are varied.
Next, referring to FIG. 1B, an oxide layer 18 is deposited at atmospheric pressure chemical vapor deposition (APCVD) on a substrate 10 to fill the interior of the shallow trenches 14a, 14b, 14c. However, due to the step coverage of the oxide layer 18, the deposited oxide layer 18 has an uneven surface and a rounded shape. Then, a photoresist layer is coated on the surface of the oxide layer 16 and patterned to form a reverse active mask 20 by photolithography. The reverse active mask 20 covers the shallow trenches 14a, 14b, 14c and is complementary to the active regions 12a, 12b, 12c, 12d. However, during the formation of the reverse active mask, misalignment causes the oxide layer 18 to cover more than the shallow trenches 14a, 14b, 14c. 
Referring to FIG. 1C, the oxide layer 18 exposed outside the reverse active mask 20 is etched until the silicon nitride layer 16 is exposed so that only a part of the silicon oxide layer 18, the silicon oxide layer 18a, is formed. After removing the reverse active mask 20, as shown in FIG. 1D, it is observable that the silicon oxide layer 18a remaining does not fully cover the shallow trenches 14a, 14b, 14c at one side of the shallow trenches 14a, 14b, 14c, therefore, forming cavities 22, but at the other side over-cover the shallow trenches 14a, 14b, 14c, forming photo-overlap 24.
Referring to FIG. 1E, the portion of the oxide layer 18a higher than the shallow trenches 14a, 14b, 14c is polished by CMP until the surface of the silicon nitride layer 16 is exposed. Therefore, the silicon nitride layer 16 and the silicon oxide layer 18a are at the same level. The profile of the silicon oxide layer 18a formed by APCVD is rather rounded and the APCVD silicon oxide layer 18a is hard to be planarized. Moreover, it is obvious that the silicon oxide layer 18a does not fully fill the shallow trenches 18a, 18b, 18c but form the cavities 22. The undesired cavities 22 may cause a kink effect and consequently short circuit or leakage current which therefore influences the yield.
As a result, it is important to overcome the problems coming after the formation of the concaves due to the misalignment of the reverse active mask during the process of CMP, especially, while nowadays the linewidth is decreasing.